Read only memories (ROMs) typically serve as a nonvolatile source of data storage. Volatile memory devices, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs) can store data, but once power is removed from such devices, the data is lost. In contrast, nonvolatile memory devices, such as ROMs, electrically programmable ROMs (EPROMs), and electrically erasable and programmable ROMs (EEPROMs) retain data in the absence of power. Because of this, nonvolatile storage devices can be particularly suited for portable battery powered applications where power conservation is at a premium. In addition, nonvolatile storage devices often function to store core system data, such as the basic input-output operating system (BIOS) that is used by an electronic system.
Many EPROMs and EEPROMs achieve nonvolatility through the use of memory cells that employ a "floating" gate structure. A floating gate is a conductive structure surrounded by an insulating material that can store charge, and thus establish a logic value. Commonly, a floating gate is disposed over the channel of a metal-oxide-semiconductor (MOS) transistor structure. In this arrangement, the charge on the floating gate can alter the threshold and/or operation of the MOS structure, and thereby establish one or more logic values.
Two mechanisms that are typically used to place charge on, or remove charge from a floating gate, include "channel" hot electron injection and Fowler-Nordheim tunneling ("tunneling"). Hot electron injection is a common programming mechanism for both EPROMs and EEPROMs memory cells that have floating gates. For example, in the case of an n-channel one-transistor (1-T) "stacked" gate EEPROM cell, the floating gate is disposed between the control gate and channel of a MOS transistor structure. In a program operation, the source is maintained at a low voltage while the drain is biased to a low positive voltage. The control gate is biased to a high positive voltage. In this arrangement, electrons are accelerated from the source toward the drain, and due to the high potential of the control gates, are swept through a dielectric into the floating gate. N-channel 1-T EEPROM cells are often preferred due to their compact size.
Tunneling can be used to program or erase an EEPROM cell. In the case of an n-channel 1-T EEPROM cell, in an erase operation, the drain can be kept floating while the control gate is maintained at a relatively high negative voltage. The source can then be pulsed to a positive voltage. With the negative voltage on the control gate and a positive voltage on the source, electrons on the floating gate can tunnel through a "tunnel" dielectric to the source.
The programming and erase operation of an EEPROM can consume considerable time. In particular, for EEPROM cells that utilize tunneling, the rate at which electrons tunnel is dependent upon the tunnel dielectric thickness and the potential created between the control gate and the substrate. The extent to which the thickness of the tunnel dielectric can be reduced is limited by process capabilities and reliability concerns. Similarly, the magnitude of the potential used to induce tunneling can be limited by charge pump capabilities and reliability concerns. Consequently, the rate at which EEPROM cells can be erased by tunneling is limited. Thus, improvements in the programming and/or erase speeds of an EEPROM have been an important goal in EEPROM designs.
The need for faster erase speeds has led to "flash" EEPROMs (sometimes referred to as flash EPROMs). Flash EEPROMs derive their name from the rapid manner in which they are erased. In a conventional EEPROM, selected memory cells are erased individually, or in limited numbers, such as bytes. Thus, the erasure of an entire conventional EEPROM can be a lengthy process. In contrast, a flash EEPROM allows the simultaneous erasure of large groups of memory cells (sometimes referred to as "blocks," "banks" or "sectors"). Some sectors may be protected, and require a specialized procedure to be accessed for erase.
While EEPROM manufacturing processes continue to improve, at the same time, dimensions continue to shrink and operating speeds continue to increase. Thus, in an attempt to create smaller and faster EEPROM devices, manufacturing defects can still occur. In order to ensure that defective devices are not supplied to customers, EEPROMs are usually tested to ensure their functionality. In the case of flash EEPROMs, due to the rate at which electrons tunnel from the floating gate to the substrate, a test erase operation can consume considerable time, particularly if there are multiple sectors that must be erased one at a time. As just one example, a common eight-megabit (8-Mb) flash EEPROM configuration includes nineteen sectors of varying sizes. In such a device, a test operation would require nineteen erase operations.
One way in which to improve the speed at which test erase operations can be performed is to employ a "chip" erase function. A chip erase function allows every sector on a flash EEPROM to be erased simultaneously. A drawback to chip erase operations is that such operations can often lead to an over-erase condition in one or more EEPROM cells. An over-erase condition exists when too much negative charge is removed from the floating gate of an n-channel 1-T EEPROM cell, resulting in the cell functioning like a depletion mode transistor. The threshold voltages of over-erased cells can be corrected by a repair step which places charge back onto a floating gate (sometimes referred to as "soft program," "heal" or "compaction"). Unfortunately, repair will add even more time onto a test operation. It is therefore highly desirable to avoid over-erasing memory cells altogether.
A second way to address over-erase is to erase on a sector by sector basis, using discrete erase pulses. In this approach, a sector will be erased with an erase pulse and then tested to see if all the memory cells in the sector have been erased. If one or more cells are not erased, a second erase pulse can be applied. This can be repeated until each memory cell in the sector is properly erased. A drawback to this "gradual" erase approach is that it consumes too much time when multiple sectors must be erased.
Yet another drawback to a chip erase operations is the amount of charge required to accomplish such an operation. As noted above, the erase operation may require the control gates of the memory cells within an EEPROM to be charged to a negative gate voltage, while the sources are charged to a positive source voltage. The negative control gate voltage of EEPROMs is usually generated on the EEPROM device itself by charge pump circuits. For large EEPROM devices that have many EEPROM cells, the amount charge necessary to erase the entire chip may exceed the capacity of the charge pump circuit
It would be desirable to provide a flash EEPROM that provides for rapid erasuree of large numbers of the memory cells, to thereby speed up the EEPROM device test process. Such an erase capability should not be overly susceptible to over-erasing memory cells, or exceed on-chip charge pump capabilities.